The present invention relates to computer memory devices. More particularly, the present invention relates to management of memory devices with drifting electrical characteristics.
Typical memory devices consist of memory cells fabricated with semiconductor materials. As memory device size continues to scale down and with the continuing drive to maintain low power consumption in memory devices, many issues arise from the limitations of the materials and their electrical properties. One such issue is the drifting of electrical characteristics utilized for reading memory states. An example of drifting read characteristics is the tendency of electric charge leakage in a capacitor memory cell.
Another example is resistance drift in phase change memory (PCM) technology. Conventionally, PCM read operations measure resistance level to distinguish memory states. The resistance levels in PCM cells have a tendency to increase over time, after programming. The resistance drift makes reading the stored data from a PCM cell challenging because resistance contrast between two adjacent (in terms of resistance levels) memory states is gradually reduced over time, and resistance of different memory states may eventually overlap.
Additionally, multi-level cell (MLC) memory technology has been employed to increase data density in memory devices. MLC memory arrays incorporate memory cells with the advantage of storing two or more digit binary values, as opposed to the traditional single-level cell (SLC) memory that stores a single digit binary value. However, resistance drift is more problematic when a PCM cell is configured with a MLC scheme than a SLC scheme because the resistance margins between neighboring resistance levels are greatly reduced in MLC.